pastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 1 day agoSome Mnemonicssh.itjust.worksimagemessage-square18fedilinkarrow-up1297arrow-down15
arrow-up1292arrow-down1imageSome Mnemonicssh.itjust.workspastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 1 day agomessage-square18fedilink
minus-square9point6@lemmy.worldlinkfedilinkarrow-up22·1 day agoI still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
I still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle